1. Field of the Invention
The present invention relates to a gate driving circuit and a display apparatus including the gate driving circuit. More particularly, the present invention relates to a gate driving circuit having substantially improved output characteristics thereof, and a display apparatus including the gate driving circuit.
2. Description of the Related Art
In general, a liquid crystal display includes a liquid crystal display panel to display a desired image thereon. The liquid crystal display panel includes a lower substrate, an upper substrate facing the lower substrate and a liquid crystal layer interposed between the lower substrate and the upper substrate. The liquid crystal display panel further includes a plurality of gate lines, a plurality of data lines and a plurality of pixels. Each pixel of the plurality of pixels is connected to a corresponding gate line of the plurality of gate lines and a corresponding data line of the plurality of data lines. A gate driving circuit outputs a gate signal to the gate lines and is directly formed on the liquid crystal display panel through a thin film process, for example.
The gate driving circuit generally includes a shift register including a plurality of stages, each stage of the plurality of stages being connected one after another, e.g., cascaded. Each stage includes a plurality of transistors which output a gate voltage to a corresponding gate line. More specifically, each stage includes a pull-up transistor connected to the gate line to output the gate voltage to the corresponding gate line.
In a gate driving circuit of the prior art, a control terminal of the pull-up transistor is connected to a Q-node in each stage. Particularly, the Q-node is maintained at an electric potential of a turn-on voltage which is greater than a threshold voltage of the pull-up transistor during a horizontal scanning period (“1H”) during which the gate voltage is maintained at a high state, e.g. a high level. Thus, during a 1H period, the gate voltage output from the pull-up transistor is maintained at a turn-on voltage level. In contrast, the Q-node is maintained at a turn-off voltage level less than the threshold voltage of the pull-up transistor in a previous period, e.g., an (n−1)H period, during which the gate voltage is maintained at a low state, e.g., a low level. Therefore, the gate voltage output from the pull-up transistor is maintained at an off-voltage level during the (n−1)H period.
Meanwhile, in the gate driving circuit of the prior art, the electric potential at the Q-node ripples at a transition time of an input clock is input to the gate driving circuit during the (n−1)H period. When the electric potential of the Q-node ripples, the gate voltage output from the pull-up transistor is also rippled during the (n−1)H period.
In order to prevent the ripple of the gate voltage output from the pull-transistor, the gate driving circuit of the prior art requires a holding transistor which holds the gate voltage at the off-voltage level during the (n−1)H period, as well as an inverter which controls turn-on and turn-off operations of the holding transistor based on the input clock. The inverter outputs one of a high level and a low level of the input clock as its output signal, based on the input clock. The holding transistor applies the off-voltage to an output terminal of the pull-up transistor in response to the output signal at the high level. Therefore, the gate voltage is held at the off-voltage level.
However, due to a signal delay, the holding transistor is not able to hold the gate voltage at the off-voltage level until after a signal delay time lapses after a time when the input clock is input to the inverter. As a result, the gate driving circuit of the prior art is not able to hold the ripple component of the gate voltage generated at the transition time of the input clock at the off-voltage level.
Thus, it is desired to develop a gate driving circuit which prevents a ripple of a gate voltage.